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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad8200 high common-mode voltage, single-supply difference amplifier features high common-mode voltage range ? v to +24 v at a 5 v supply voltage operating temperature range die: ?0 c to +150 c supply voltage range: 4.7 v to 12 v low-pass filter (one pole or two pole) excellent ac and dc performance 1 mv voltage offset 10 ppm/ c typ gain drift 80 db cmrr min dc to 10 khz platforms transmission control diesel injection control engine management adaptive suspension control vehicle dynamics control functional block diagram soic (r) package die form a1 +in ?n 200k 200k 100k a2 +in ?n g = 10 g = 2 ad8200 10k 10k +in ?n out gnd nc a1 a2 +v s nc = no connect general description the ad8200 is a single-supply difference amplifier for amplifying and low-pass filtering small differential voltages in the presence of a large common-mode voltage. the input cmv range extends from ? v to +24 v at a typical supply voltage of 5 v. the ad8200 is offered in die and packaged form. both package options are specified over wide temperature ranges, making the ad8200 well suited for use in many automotive platforms. the soic package is specified over a temperature range of ?0 c to +125 c. the die is specified from ?0 c to +150 c. automotive platforms demand precision components for better system control. the ad8200 provides excellent ac and dc per- formance that keeps errors to a minimum in the user? system. typical offset and gain drift in the soic package are 6 v/ c and 10 ppm/ c, respectively. the device also delivers a mini- mum cmrr of 80 db from dc to 10 khz. the ad8200 features an externally accessible 100 k ? resistor at the output of the preamp a1, which can be used for low-pass filter applications and for establishing gains other than 20. gnd nc ?n +in a1 +v s a2 out ad8200 5v output inductive load power device 4 term shunt clamp diode battery 14v common nc = no connect figure 1. high line current sensor 5v output inductive load 4 term shunt clamp diode battery 14v power device common nc = no connect gnd nc ?n +in a1 +v s a2 out ad8200 figure 2. low line current sensor
rev. b e2e ad8200especifications single supply ad8200 soic ad8200 die parameter condition min typ max min typ max unit system gain initial 20 20 v/v error v o 0.1 v dc e1 +1 e1 +1 % vs. temperature 10 20 25 30 ppm/ c voltage offset input offset (rti) v cm = 0.15 v; 25 ce1 +1e1 +1mv v cm = 0.15 v; 125 c (soic) +150 c (die) e2.5 +2.5 e3.5 +3.5 mv v cm = 0.15 v; e40 ce2 +2e3 +3mv input input impedance differential 320 400 480 320 400 480 k common-mode 160 200 240 160 200 240 k cmv continuous e2 +24 e2 +24 v common-mode rejection 1 v cm = 10 v f = 1 khz 80 80 db f = 10 khz 2 80 80 db preamplifier gain 10 10 v/v gain error e1 +1 e1 +1 % output voltage range 0.02 4.8 0.02 4.8 v output resistance 97 100 103 97 100 103 k output buffer gain 2 2 v/v gain error e1 +1 e1 +1 % output voltage range 0.02 4.8 0.02 4.8 v output resistance 2 2 dynamic response 3 db bandwidth 30 50 30 50 khz slew rate 0.22 0.22 v/ s noise 0.1 hz to 10 hz 10 10 v p-p spectral density, 1 khz, rti 300 300 nv/ hz hzh
rev. b ad8200 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8200 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 v transient input voltage (300 ms) . . . . . . . . . . . . . . . . . . 44 v continuous input voltage . . . . . . . . . . . . . . . . . . . . . . . . 35 v reversed supply voltage protection . . . . . . . . . . . . . . . . 0.3 v operating temperature die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c to +150 c soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c output short-circuit duration . . . . . . . . . . . . . . . . indefinite lead temperature range (soldering 60 sec) . . . . . . . . . 300 c * stresses beyond those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package description package option ad8200yr ?0 c to +125 c soic r-8 ad8200yr-reel ?0 c to +125 c soic r-8 ad8200yr-reel-7 ?0 c to +125 c soic r-8 AD8200YCHIPS ?0 c to +150 cdie form ad8200ycsurf ?0 c to +150 cdie form pin configuration top view (not to scale) 8 7 6 5 1 2 3 4 nc = no connect ?n gnd a1 a2 +in nc +v s out ad8200 metallization photograph +in ?n 1 8 gnd 2 a1 3 +v s 6 out 5 a2 4
rev. b e4e ad8200etypical performance characteristics supply voltage e v 0 25 3 positive common-mode range e v 4 5 10 15 20 25 30 e12 negative common-mode range e v e10 e8 e6 e4 e2 0 +v cm ev cm tpc 1. input common-mode range vs. supply supply voltage e v e35 2 5 3 output voltage e mv 4 e30 0 e25 e20 e15 e10 e5 r l = r l = 10k to gnd tpc 2. output voltage e v s vs. supply load resistance e 5 0 10 output voltage e v 100 1k 10k 1 2 3 4 tpc 3. output voltage swing vs. load resistance frequency e hz 30 e20 1k gain e db 10k 100k 1m 0 e15 e10 e5 5 10 15 20 25 tpc 4. gain vs. frequency frequency e hz 100 50 10 cmrr e db 1k 10k 1m 70 55 60 65 75 80 85 90 95 100 100k tpc 5. common-mode rejection ratio vs. frequency frequency e hz 100 0 10 psrr e db 40 10 20 30 50 60 70 80 90 100 10k 1k 100k tpc 6. power supply rejection ratio vs. frequency (t a = 25 c, v s = 5 v, v cm = 0 v, r l = 10 k , unless otherwise noted.)
rev. b ad8200 e5e theory of operation the ad8200 consists of a preamp and buffer arranged as shown in figure 3. like-named resistors have equal values. the preamp incorporates a dynamic bridge (subtractor) circuit. identical networks (within the shaded areas), consisting of r a , r b , r c , and r g , attenuate input signals applied to pins 1 and 8. note that when equal amplitude signals are asserted at inputs 1 and 8, and the output of a1 is equal to the common potential (i.e., zero), the two attenuators form a balanced-bridge network. when the bridge is balanced, the differential input voltage at a1, and thus its output, will be zero. any common-mode voltage applied to both inputs will keep the bridge balanced and the a1 output at zero. because the resistor networks are carefully matched, the common-mode signal rejec- tion approaches this ideal state. however, if the signals applied to the inputs differ, the result is a difference at the input to a1. a1 responds by adjusting its output to drive r b , by way of r g , to adjust the voltage at its inverting input until it matches the voltage at its noninverting input. by attenuating voltages at pins 1 and 8, the amplifier inputs are held within the power supply range, even if pin 1 and pin 8 input levels exceed the supply, or fall below common (ground.) the input network also attenuates normal (differential) mode voltages. r c and r g form an attenuator that scales a1 feedback, forcing large output signals to balance relatively small differen- tial inputs. the resistor ratios establish the preamp gain at 10. because the differential input signal is attenuated, and then amplified to yield an overall gain of 10, the amplifier a1 oper- ates at a higher noise gain, multiplying deficiencies such as input offset voltage and noise with respect to pins 1 and 8. a1 a3 r cm r cm (trimmed) 100k r a ein r g r c r b r a r c r b r g +in com a2 r f r f ad8200 figure 3. simplified schematic to minimize these errors while extending the common-mode range, a dedicated feedback loop is employed to reduce the r ange of common-mode voltage applied to a1, for a given over- all range at the inputs. by offsetting the range of voltage applied to the compensator, the input common-mode range is also offset to include voltages more negative than the power supply. ampli- fier a3 detects the common-mode signal applied to a1 and adjusts the voltage on the matched r cm resistors to reduce the common-mode voltage range at the a1 inputs. by adjusting the common voltage of these resistors, the common-mode input range is extended while, at the same time, the normal mode signal attenuation is reduced, leading to better performance referred to input. the output of the dynamic bridge taken from a1 is connected to pin 3 by way of a 100 k series resistor, provided for low- pass filtering and gain adjustment. the resistors in the input networks of the preamp and the buffer feedback resistors are ratio-trimmed for high accuracy. the output of the preamp drives a gain-of-two buffer-amplifier a2, implemented with carefully matched feedback resistors r f . the two-stage system architecture of the ad8200 enables the user to incorporate a low-pass filter prior to the output buffer. by separating the gain into two stages, a full-scale rail-to-rail signal from the preamp can be filtered at pin 3, and a half-scale signal resulting from filtering can be restored to full scale by the output buffer amp. the source resistance seen by the inverting input of a2 is approximately 100 k , to minimize the effects of a2?s input bias current. however, this current is quite small and errors resulting from applications that mismatch the resistance are correspondingly small. applications the ad8200 difference amplifier is intended for applications where it is required to extract a small differential signal in the presence of large common-mode voltages. the input resistance is nominally 200 k , and the device can tolerate common-mode voltages higher than the supply voltage and lower than ground. the open collector output stage will source current to within 20 mv of ground. 2 1 tek run: 2.5ms/s hi res v out , r l = 10k t v in ch1 500mv 50mv m 20 s ch1 1.5v ch2 tpc 7. pulse response 3 1 tek run: 2.5ms/s average v in ch3 100mv v out , r l = 10k magnified v out 2 ch1 1v ch 2 10mv m 20 s ch1 1.36v tpc 8. settling time
rev. b e6e ad8200 current sensing high line, high current sensing basic automotive applications making use of the large common- mode range are shown in figures 1 and 2. the capability of the device to operate as an amplifier in primary battery supply circuits is shown in figure 1; figure 2 illustrates the ability of the device to withstand voltages below system ground. low current sensing the ad8200 can also be used in low current sensing applica- tions, such as the 4e20 ma current loop shown in figure 4. in such applications, the relatively large shunt resistor can degrade the common-mode rejection. adding a resistor of equal value in the low impedance side of the input corrects for this error. 5v output 10 10 1% nc = no connect 1% + gnd nc ein +in a1 +v s a2 out ad8200 figure 4. 4e20 ma current loop receiver gain adjustment the default gain of the preamplifier and buffer are 10 and 2, respectively, resulting in a composite gain of 20. with the addition of external resistor(s) or trimmer(s), the gain may be lowered, raised, or finely calibrated. gains less than 20 since the preamplifier has an output resistance of 100 k , an exter- nal resistor connected from pins 3 and 4 to gnd will decrease the gain by a factor r ext /(100 k + r ext ) (see figure 5). 10k 10k 100k a2 a1 gnd ein out +v s nc +in ad8200 out +v s r ext v cm v diff 2 gain = 20r ext r ext + 100k r ext = 100k gain 20 e gain v diff 2 nc = no connect figure 5. adjusting for gains less than 20 the overall bandwidth is unaffected by changes in gain using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to the buffer. in many cases this can be ignored, but if desired, can be nulled by inserting a resistor equal to 100 k minus the parallel sum of r ext and 100 k , in series with pin 4. for example, with r ext = 100 k (yielding a composite gain of 10), the optional offset nulling resistor is 50 k (see figure 11.) gains greater than 20 connecting a resistor from the output of the buffer amplifier to its noninverting input, as shown in figure 6, will increase the gain. the gain is now multiplied by the factor r ext /(r ext e 100 k ); for example, it is doubled for r ext = 200 k . overall gains as high as 50 are achievable in this way. note that the accuracy of the gain becomes critically dependent on resistor value at high gains. also, the effective input offset voltage at pins 1 and 8 (about six times the actual offset of a1) limits the part?s use in very high gain, dc-coupled applications. 10k 10k 100k a2 a1 ein +v s nc +in ad8200 gnd out out +v s v cm gain = 20r ext r ext e 100k r ext = 100k gain gain e 20 r ext v diff 2 v diff 2 nc = no connect figure 6. adjusting for gains greater than 20 gain trim figure 7 shows a method for incremental gain trimming using a trimpot and external resistor r ext . the following approximation is useful for small gain ranges gmr ext () 10 % thus, the adjustment range would be 2% for r ext = 5 m ; 10% for r ext = 1 m , and so on. 5v out r ext gain trim 20k min v cm v diff 2 v diff 2 nc = no connect gnd nc ein +in a1 +v s a2 out ad8200 figure 7. incremental gain trim
rev. b ad8200 e7e internal signal overload considerations when configuring gain for values other than 20, the maximum input voltage with respect to the supply voltage and ground must be considered, since either the preamplifier or the output buffer will reach its full-scale output (approximately v s e 0.2 v ) with large differential input voltages. the input of the ad8200 is limited to ( v s e 0.2) 10, for overall gains 10, since the preamplifier, with its fixed gain of 10, reaches its full-scale output before the output buffer. for gains greater than 10, the swing at the buffer output reaches its full scale first and limits the ad8200 input to ( v s e 0.2) g , where g is the overall gain. low-pass filtering in many transducer applications, it is necessary to filter the signal to remove spurious high frequency components, including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (par) greater than unity. for example, a full-wave rectified sinusoid has a par of 1.57, a raised cosine has a par of 2, and a half-wave sinusoid has a par of 3.14. signals having large spikes may have pars of 10 or more. when implementing a filter, the par should be considered so the output of the ad8200 preamplifier (a1) does not clip before a2, since this nonlinearity would be averaged and appear as an error at the output. to avoid this error, both amplifiers should be made to clip at the same time. this condition is achieved when the par is no greater than the gain of the second ampli- fier (2 for the default configuration). for example, if a par of 5 is expected, the gain of a2 should be increased to 5. low-pass filters can be implemented in several ways using the features provided by the ad8200. in the simplest case, a single- pole filter (20 db/decade) is formed when the output of a1 is connected to the input of a2 via the internal 100 k resistor by strapping pins 3 and 4 and a capacitor added from this node to ground, as shown in figure 8. if a resistor is added across the capacitor to lower the gain, the corner frequency will increase; it should be calculated using the parallel sum of the resistor and 100 k . 5v c v cm out f c = 1 2 c10 5 c in farads v diff 2 v diff 2 nc = no connect gnd nc ein +in a1 +v s a2 out ad8200 figure 8. a single-pole, low-pass filter using the internal 100 k resistor if the gain is raised using a resistor, as shown in figure 8, the corner frequency is lowered by the same factor as the gain is raised. thus, using a resistor of 200 k (for which the gain would be doubled), the corner frequency is now 0.796 hz- f, (0.039 f for a 20 hz corner frequency.) out v cm c 255k c f c = 1hz e f 5v nc = no connect v diff 2 v diff 2 gnd nc ein +in a1 +v s a2 out ad8200 figure 9. 2-pole low-pass filter a 2-pole filter (with a roll-off of 40 db/decade) can be implemented using the connections shown in figure 9. this is a sallen-key form based on a 2 amplifier. it is useful to remember that a 2-pole filter with a corner frequency f 2 and a 1-pole filter with a corner at f 1 have the same attenuation at the frequency (f 2 2 /f 1 ). the attenuation at that frequency is 40 log (f 2 /f 1 ). this is illustrated in figure 10. using the standard resistor value shown and equal capacitors (figure 9), the corner frequency is conveniently scaled at 1 hz- f (0.05 f for a 20 hz corner). a maximally flat response occurs when the resistor is lowered to 196 k and the scaling is then 1.145 hz- f. the output offset is raised by approximately 5 mv (equivalent to 250 v at the input pins). 40log (f 2 /f 1 ) f 1 attenuation f 2 f 2 2 /f 1 frequency a 1-pole filter, corner f 1 , and a 2-pole filter, corner f 2 , have the same attenuation e40log (f 2 /f 1 ) at frequency f 2 2 /f 1 20db/decade 40db/decade figure 10. comparative responses of 1-pole and 2-pole low-pass filters
rev. b e8e ad8200 high-line current sensing with lpf and gain adjustment figure 11 is another refinement of figure 1, including gain adjustment and low-pass filtering. 5v output 4v/amp inductive load power device 4 term shunt clamp diode battery 14v common c v os/ib null 191k 20k 5% calibration range f c = 0.796hze f ( 0.22 f for f = 3.6 hz) nc = no connect gnd nc ein +in a1 +v s a2 out ad8200 figure 11. high-line current sensor interface; gain = 40, single-pole, low-pass filter a power device that is either on or off controls the current in the load. the average current is proportional to the duty cycle of the input pulse and is sensed by a small value resistor. the average differential voltage across the shunt is typically 100 mv, although its peak value will be higher by an amount that depends on the inductance of the load and the control frequency. the common-mode voltage, on the other hand, extends from roughly 1 v above ground, when the switch is on, to about 1.5 v above the battery voltage, when the device is off, and the clamp diode conducts. if the maximum battery voltage spikes up to 20 v, the common-mode voltage at the input can be as high as 21.5 v. to produce a full-scale output of 4 v, a gain 40 is used, adjust- able by 5% to absorb the tolerance in the shunt. there is sufficient headroom to allow 10% overrange (to 4.4 v). the roughly triangular voltage across the sense resistor is averaged by a 1-pole, low-pass filter, here set with a corner frequency = 3.6 hz, which provides about 30 db of attenuation at 100 hz. a higher rate of attenuation can be obtained using a 2-pole filter having f c = 20 hz, as shown in figure 12. although this circuit uses two separate capacitors, the total capacitance is less than half that needed for the 1-pole filter. 5v output inductive load power device 4 term shunt clamp diode battery 14v common c 127k 432k 50k f c = 1hze f ( 0.05 f for f c = 20hz) c nc = no connect gnd nc ein +in a1 +v s a2 out ad8200 figure 12. illustration of 2-pole low-pass filtering driving charge redistribution a/d converters when driving cmos adcs, such as those embedded in popular microcontrollers, the charge injection ( q) can cause a significant deflection in the output voltage of the ad8200. though generally of short duration, this deflection may persist until after the sample period of the adc has expired, due to the relatively high open-loop output impedance of the ad8200. including an r-c network in the output can significantly reduce the effect. the capacitor helps to absorb the transient charge, effectively lowering the high frequency output impedance of the ad8200. for these applications, the output signal should be taken from the midpoint of the r lag e c lag combination as shown in figure 13. since the perturbations from the analog-to-digital converter are small, the output impedance of the ad8200 will appear to be low. the transient response will, therefore, have a time constant governed by the product of the two lag components, c lag r lag . for the values shown in figure 13, this time constant is programmed at approximately 10 s. therefore, if samples are taken at several tens of microseconds or more, there will be negligible charge stack-up. +in ein 10k 10k ad8200 5v r lag 1k c lag 0.01 f microprocessor a/d a2 figure 13. recommended circuit for driving cmos a /d
rev. b ad8200 ? outline dimensions 8-lead standard small outline package [soic] narrow body (r-8) dimensions shown in millimeters and (inches) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 85 4 1 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012aa
rev. b e10e ad8200 revision history location page 11/03?data sheet changed from rev. a to rev. b. change to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 change to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 change to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6/02?data sheet changed from rev. 0 to rev. a. change to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
e11e
c02054e0e11/03(b) e12e

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